Constraint Solving over Multi-Valued Logics: Application to by Francisco Azevedo
By Francisco Azevedo
Platforms are topic to faults of their elements, affecting their total behaviour. In a "black-box" procedure, such faults purely develop into obvious within the output whilst acceptable inputs are given, which poses a couple of pride and optimization difficulties relating to either checking out and diagnosing. This paintings addresses such difficulties constructing types with multi-valued logics that it formalizes and generalizes to a number of faults. Such logics expand Boolean common sense by means of encoding dependencies on faults, therefore permitting the modelling of an arbitrary variety of diagnostic theories. The effectiveness of constraint fixing over finite domain names and units is proven on numerous difficulties.
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Extra resources for Constraint Solving over Multi-Valued Logics: Application to Digital Circuits
The cardinality of the circuit test set). The total time needed is shown in seconds, as well as the average time per test generation (T/TG) attempted. 4. 908 c2670 c3540 c5315 c6288 c7552 Red. Ab. 2 88 122 281 9924 As with other ATG systems, emphasis is given to finding a small test set while assuring high fault coverage. Test sets may be much smaller than the whole set of faults since a test may detect many faults, as previously explained. The general idea of the ATG system is to generate a test pattern for one of the still undetected faults and, if successful, perform fault simulation in the circuit with the obtained test to check what other faults are also detected (such simulation is discussed in Chapter 5).
6 Summary This chapter presented combinational digital circuits as the global subject of the problems and examples that will be covered throughout this thesis, and our general modelling approach for them considering the possible faults that may affect their behaviour. The next chapter presents a basic problem (testing) involving some possible fault(s) in the circuit, and discusses and compares approaches and algorithms for circuit or fault testing. e. output an incorrect function), it is important to know whether it is normal or faulty, so that its output can be trusted.
G. c432 of [ISCAS 1985]), which, even if relatively small, create a number of difficulties hard to handle. Note that the above mentioned TG algorithms also face this problem. Applying the single-path sensitisation restriction here may largely compensate in terms of time by reducing backtracking, but, as mentioned, at the possible cost of not finding the solution even if one exists. 2 CLP(FD) In [Simonis 1992], the author presents another TG version for CHIP, where fault propagation is not always enforced, and where two extra symbolic values: e and enot are introduced.